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Hy Ad001 User Manual Transmission

• Page 1: User Guide

  Integrator/IM-AD1 User Guide Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
• Page 2 Integrator/IM-AD1 User Guide Copyright © 2001-2003. All rights reserved. Release Information Date Oct 2001 Nov 2003 Proprietary Notice Words and logos marked with as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.
• Page 3 Conformance Notices This section contains conformance notices. Federal Communications Commission Notice This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c). CE Declaration of Conformity The system should be powered down when not in use. The Integrator generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications.
• Page 4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.

• Page 5: Table Of Contents

  Hardware Reference ARM DUI 0163B About this book . viii Feedback . xi About the Integrator/IM-AD1 . 1-2 Interface module features and architecture . 1-4 Links and LEDs . 1-6 Care of modules . 1-7 Fitting the interface module . 2-2 Setting up the logic module .
• Page 6 Contents Chapter 4 Reference Design Example 4.10 4.11 4.12 4.13 Appendix A Signal Descriptions Appendix B Mechanical Specification Glossary CAN interface . 3-14 ADC and DAC interfaces . 3-18 About the design example . 4-2 Example APB register peripheral . 4-8 UART .

• Page 7: Preface

  Preface This preface introduces the Integrator/IM-AD1 interface module and its user documentation. It contains the following sections: • About this book on page viii • Feedback on page xi. ARM DUI 0163B Copyright © 2001-2003. All rights reserved.

• Page 8: About This Book

  Preface About this book This book provides user information for the ARM Integrator/IM-AD1 interface module. It describes the major features and how to use the interface module with an Integrator development platform. Intended audience This book is written for all developers who are using an Integrator/LM logic module to develop ARM-based devices.
• Page 9 Typographical conventions The following typographical conventions are used in this book: italic bold monospace monospace monospace italic monospace bold Further reading This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors. ARM periodically provides updates and corrections to its documentation.
• Page 10 The following publication provides information about Multi-ICE: • Multi-ICE User Guide (ARM DUI 0048). Third-party documents The following documents provide information about third-party components used on the Integrator/IM-AD1: • CC770 Stand Alone CAN Controller Target Specification Robert Bosch GmbH •.

• Page 11: Feedback

  Feedback ARM Limited welcomes feedback on both the Integrator/IM-AD1 and its documentation. Feedback on this document If you have any comments on this book, please send email to • the document title • the document number • the page number(s) to which your comments apply •.
• Page 12 Preface Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
• Page 13 Chapter 1 Introduction This chapter introduces the Integrator/IM-AD1. It contains the following sections: • About the Integrator/IM-AD1 on page 1-2 • Interface module features and architecture on page 1-4 • Links and LEDs on page 1-6 • Care of modules on page 1-7.

• Page 14: Chapter 1 Introduction

  The interface module is designed to be mounted on top of the logic module and provides connectivity for peripherals in the logic module FPGA. Figure 1-1 on page 1-3 shows the layout of the IM-AD1 and identifies the connectors. The IM-AD1 can be used to implement additional peripherals to aid software development, for example additional timers or a vector interrupt controller.
• Page 15 (J7) ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Introduction Stepper motor control (J19 and J20) SPI2 (J13) SPI1 (J11) D/A Outputs (J2) GPIO A (J17) GPIO B (J16) A/D Inputs (J1) (J3A and J3B)) Figure 1-1 Integrator/IM-AD1 layout.

• Page 16: Interface Module Features And Architecture

  Introduction Interface module features and architecture This section describes the main features of the interface module and its architecture. 1.2.1 Features The main features of the interface module are as follows: • two Bosch CC770 Controller Area Network (CAN) controllers •.
• Page 17 Chapter 3 Hardware Reference. ARM DUI 0163B Stepper motor interfaces CAN interfaces D to A converter A to D converter PWMs UART interface Figure 1-2 Integrator/IM-AD1 block diagram Copyright © 2001-2003. All rights reserved. Introduction.

• Page 18: Links And Leds

  Introduction Links and LEDs The interface module provides one link and one LED. These are the CONFIG link and CONFIG LED. Fitting the CONFIG link places all of the modules in the stack on which the interface module is mounted into CONFIG mode. This mode enables you to reprogram the FPGA image in the configuration flash on the logic module(s) using Multi-ICE (see the user guide for the logic module).

• Page 19: Care Of Modules

  Care of modules This section contains advice about how to prevent damage to your Integrator modules. To prevent damage to your Integrator system, observe the following precautions: • When removing a core or logic module from a motherboard, or when separating modules, take care not to damage the connectors.
• Page 20 Introduction Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.

• Page 21: Chapter 2 Getting Started

  Chapter 2 Getting Started This chapter describes how to set up and start using the logic module. It contains the following sections: • Fitting the interface module on page 2-2 • Setting up the logic module on page 2-3 • Running the test software on page 2-4 ARM DUI 0163B Copyright ©.

• Page 22: Fitting The Interface Module

  Getting Started Fitting the interface module The interface module is installed at the top of a stack of up to four logic modules. However, it only provides interface connections for the logic module immediately beneath it. Figure 2-1 shows an example system comprising a core module and logic module attached to an Integrator/AP (see the Integrator/AP User Guide for more details).

• Page 23: Setting Up The Logic Module

  Switch 3 Open Switch 4 Open. The logic module will now be configured with the example design. If the IM-AD1 is not already fitted, install it on top of the logic module and the system is ready to use. ARM DUI 0163B Install_directoryIM-AD1configure program file.

• Page 24: Running The Test Software

  Getting Started Running the test software The supplied test program tests each of the interfaces on the IM-AD1. The example logic module configuration must be programmed into the logic module before the test program can be run. The test software requires various cables to be connected to the IM-AD1, details of.
• Page 25 Chapter 3 Hardware Reference This chapter describes the hardware interfaces and controllers on the interface module. This chapter contains the following sections: • Differences in signal routing between supported logic modules on page 3-2 • UART interface on page 3-3 •.

• Page 26: Differences In Signal Routing Between Supported Logic Modules

  Hardware Reference Differences in signal routing between supported logic modules The Integrator/LM-XCV600E+ and LM-EP20K600E+ logic module types route the signals from the interface module differently as follows: • LM-XCV600E+ is fitted with a Xilinx FPGA and routes the interface module ABANK[59:0] signals to bank 0 on the FPGA and the BBANK[53:0] signals to bank 1 on the FPGA.

• Page 27: Uart Interface

  UART interface The interface module provides one serial transceiver suitable for use with the PrimeCell UART (PL011) or other similar peripheral. Figure 3-1 shows the architecture of the UART interface. The signals associated with the UART interface are assigned to the EXPIM socket pins as shown in Table 3-1.
• Page 28 Hardware Reference The serial interface uses a 9-pin D-type male connector for which the pin numbering is shown in Figure 3-2. Table 3-2 shows the signal assignment for the connector. The serial interfaces signals operate at RS232 signal levels. Serial port functionality corresponds to the DTE configuration. Table 3-2 Serial connector signal assignment SER_DCD SER_RXD.

• Page 29: Spi

  This interface module provides two connectors for SPI ports. They are connected directly to the logic module FPGA and are used by the SSP PrimeCell (PL022) in the example configuration. Table 3-3 shows the assignment of the SPI signals to the logic module signals on the EXPIM connector.

• Page 30: Pwm Interface

  Hardware Reference PWM interface The interface module is fitted with a dual MOSFET switch. This provides two outputs that can be configured as Pulse Width Modulated (PWM) outputs or used as DC switches to switch external loads. The MOSFET can switch loads at up to 30V. Although the MOSFET is rated for 3A, because of the power dissipation of the package the maximum load current is 2.5A if only one PWM output is used or 1.75A if both outputs are used.
• Page 31 Table 3-5 shows the signal assignment. ARM DUI 0163B PWM1_+V PWM2_+V PWM1_SWITCH PWM2_SWITCH PWM1_FB PWM2_FB PWM_GND PWM_GND Copyright © 2001-2003. All rights reserved. Hardware Reference Table 3-5 PWM connector signals Description PWM supply voltage PWM switched load connection PWM feedback signal PWM ground.

• Page 32: Stepper Motor Interface

  Hardware Reference Stepper motor interface The IM-AD1 provides four stepper motor interfaces. Two of these, Step 1 and Step 2, are provided with on-board motor drivers for bipolar motors. The remaining two, Step 3 and Step 4, provide logic-level signals that are connected to two 10-pin headers. This enables you to connect to off-board motor drivers.
• Page 33 The current limit is set by the reference voltage and sense resistor according to the equation: peak Therefore, with a 0.1Ω sense resistor fitted: = 0.15 x 10 = 1.5A peak The reference voltage, and therefore the current limit, can be adjusted by altering the values of the divider resistors.
• Page 34 Hardware Reference Signal STEP2_PH1 STEP2_PH2 STEP2_PH3 STEP2_PH4 STEP3_ENA STEP3_ENB STEP3_PH1 STEP3_PH2 STEP3_PH3 STEP3_PH4 STEP4_ENA STEP4_ENB STEP4_PH1 STEP4_PH2 STEP4_PH3 STEP4_PH4 3.5.3 Stepper motor connectors Figure 3-6 shows the pin numbering of the stepper motor connectors. 3-10 Table 3-6 Stepper motor interface signals (continued) EXPB Description connector.
• Page 35 Table 3-7 shows the signal assignment. ARM DUI 0163B STEP1_VSS STEP2_VSS STEP1_O1 STEP2_O1 STEP1_O2 STEP2_O2 STEP1_O3 STEP2_O3 STEP1_O4 STEP2_O4 STEP_GND STEP_GND Copyright © 2001-2003. All rights reserved. Hardware Reference Table 3-7 Stepper motor connector signals Description Stepper motor supply Stepper motor drive output 1 Stepper motor drive output 2 Stepper motor drive output 3 Stepper motor drive output 4.

• Page 36: Gpio

  Hardware Reference GPIO The interface module provides two connectors for GPIO interfaces. Each connector provides 32 GPIO lines connected directly to the logic module FPGA. The connectors are shown in Figure 3-7. 3-12 +3V3 GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOA8.
• Page 37 Hardware Reference The example configuration includes two simple 32-bit GPIO controllers. GPIOA[31:0] connect to the EXPIM signals IM_ABANK[31:0] and GPIOB[31:0] connects to the EXPA signals B[31:0]. The B[31:0] signals can be monitored on the logic analyzer connector J7. ARM DUI 0163B Copyright ©.

• Page 38: Can Interface

  Hardware Reference CAN interface The IM-AD1 has two CAN interfaces provided by Bosch CC770 serial communications controllers. The network interfaces are provided by Philips TJA1050 transceivers, each capable of 1Mb/s data transfer. Figure 3-8 shows the architecture of the CAN interface. The CAN controllers are 5V devices and are supported by buffers at their interface with the 3.3V system buses.
• Page 39 All interface signals are routed to the logic module. The CAN controllers are supported by an AHB interface instantiated into the logic module code example supplied with the IM-AD1. The transmit and receive data signals, CANx_TXD and CANx_RXD, at the EXPIM connectors are not used for the normal operation of the interfaces.
• Page 40 Hardware Reference You connect the CAN interfaces through the 9-pin D-type plugs J3A (top) and J3B (bottom), with CAN1 connecting to J3A. Figure 3-9 shows the pin locations for this type of connector. 3-16 Table 3-8 CAN interface signal assignment (continued) EXPIM Signal connector.
• Page 41 Table 3-9 shows the signal assignment. ARM DUI 0163B Table 3-9 CAN connector signal assignments Copyright © 2001-2003. All rights reserved. Hardware Reference Not connected Not connected CAN1_L CAN2_L Not connected Not connected CAN1_H CAN2_H Not connected Not connected Not connected Not connected 3-17.

• Page 42: Adc And Dac Interfaces

  DAC_nWR All of the interface signals are routed to the FPGA on the logic module. The ADCs and DAC are supported by an AHB interface that is instantiated in the logic module code example supplied with the IM-AD1. 3-18 AD_D[15:0]_5V.
• Page 43 Table 3-10 shows the assignment of the ADC and DAC interface signals to the logic module signals on the EXPIM connector. Signal AD_D[15:0] AD_T/R AD_nOE ADC1_nCONV ADC1_nCS ADC1_nWR ADC1_nRD ADC2_nCONV ADC2_nCS ADC2_nWR ADC2_nRD ADC1_BUSY ADC2_BUSY DAC_nCLR DAC_nLDAC DAC_A0 DAC_nCS DAC_nWR ADC_CLK The ADCs are clocked from a 4MHz oscillator.
• Page 44 Hardware Reference The analog inputs to the ADCs are buffered by LMV324 operational amplifiers (op-amps). The op-amps are configured to give unity gain but the inputs have a resistive divider that divides the input voltage by 2. A 0-5V input signal range at the buffer inputs provides a 0-2.5V full range at the ADC input.
• Page 45 Figure 3-12 shows the pinout of the DAC interface connector (J2). ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Hardware Reference VOUTA VOUTB Figure 3-12 DAC connector pinout 3-21.
• Page 46 Hardware Reference 3-22 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
• Page 47 Chapter 4 Reference Design Example This chapter describes how to set up and start using the supplied example design. It contains the following sections: • About the design example on page 4-2 • Example APB register peripheral on page 4-8 •.

• Page 48: About The Design Example

  Reference Design Example About the design example This chapter describes the reference design example supplied with the interface module. The interface module is not fitted with any programmable devices because it is intended to provide interfaces for peripherals instantiated into a logic module FPGA. The interface module design example for the logic module is supplied in VHDL.
• Page 49 System Table 4-1 provides a summary description of the supplied VHDL files. A more detailed description of each VHDL block is included within the files in the form of comments. File Description This file is the top-level VHDL that instantiates all of the interface for the example. The VHDL for IMAD1fpga the PrimeCell interfaces are not supplied but are available from ARM as separate products.
• Page 50 Reference Design Example File Description This is the AHB multiplexor that connects the read data buses and the HRESP and HREADY AHBMux7S1M signals from all of the slaves to the AHB master. AHBZBTRAM An SSRAM controller block to support word, halfword, and byte operations to the SSRAM on the logic module.
• Page 51 0xF0000000 0xE0000000 0xD0000000 0xC0000000 The Integrator system implements a distributed address decoding scheme in which each core or logic module is responsible for decoding its own address space. It is important when implementing a logic module design, to ensure that the module responds to all memory accesses in the appropriate memory region (see the user guide for your motherboard).
• Page 52 Guide for more information). 4.1.5 Integrator/IM-AD1 memory map The memory model for the design is shown in Table 4-2 and assumes that the logic module is mounted in position 0. Table 4-3 Integrator/IM-AD1 memory map Device logic module APB registers UART0 SPICS.
• Page 53 ARM DUI 0163B Table 4-3 Integrator/IM-AD1 memory map (continued) Device STEPPERB GPIOA GPIOB Reserved SSRAM ADC/DAC Copyright © 2001-2003. All rights reserved. Reference Design Example Address 0xC0C00000 0xC0D00000 0xC0E00000 0xC1000000 0xC2000000 0xC3000000 0xC4000000 0xC5000000 0xCFFFFF00.

• Page 54: Example Apb Register Peripheral

  Reference Design Example Example APB register peripheral Table 4-4 shows the mapping of the logic module registers. The addresses shown are offsets from the base addresses shown in Figure 4-2 on page 4-5. Offset address 0x0000000 0x0000004 0x0000008 0x000000C 0x0000010 0x0000014 Name Type.
• Page 55 4.2.1 Oscillator divisor registers The oscillator registers control the frequency of the clocks generated by the two clock generators on the logic module. Before writing to the oscillator registers, you must unlock them by writing the value 0x0000A05F by writing any value other than The reference divider (R[6:0]) and VCO divider (V[8:0]) are used to calculate the output frequency as follows: Frequency = 48MHz ·.
• Page 56 Reference Design Example You must also observe the operating range limits: 10MHz < 48MHz · R[6:0] < 118 Bits 18:16 15:9 The default values for these registers set CLK1 to 25MHz and CLK2 to 12MHz. 4-10 (V[8:0] +8) (R[6:0] +2) Name Access Function.
• Page 57 4.2.2 Oscillator lock register The lock register is used to control access to the oscillator registers, allowing them to be locked and unlocked. This mechanism prevents the oscillator registers from being overwritten accidently. Table 4-6 describes the lock register bits. Bits 15:0 4.2.3.
• Page 58 Reference Design Example 4.2.5 Switches register This register is used to read the setting of the 8-way DIP switch on the logic module. A 0 indicates that the associated switch element is closed (ON). 4-12 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.

• Page 59: Uart

  UART The UART used in the design example is the PrimeCell PL011. Refer to the ARM PrimeCell UART (PL011) Technical Reference Manual for more information. The UART is clocked by the signal CLK2 from the logic module. CLK2 is set to 12MHz by default.

• Page 60: Spi Chip Select Register

  Reference Design Example SPI chip select register This is a 3-bit read/write register that controls the three chip select signals on the connectors J11 and J13. Writing a 1 causes the associated SPI chip select signal to go LOW. 4-14 Table 4-8 SPI chip select register bit assignment Name Access.

• Page 61: Synchronous Serial Port

  Synchronous serial port The synchronous serial port PrimeCell is used to implement the SPI interface. Refer to the ARM PrimeCell Synchronous Serial Port Master and Slave (PL022) Technical Reference Manual for information about this device. The SSP is clocked by the CLK1 signal from the logic module. This clock is set to 25MHz by default.

• Page 62: Pwm Controller

  Reference Design Example PWM controller The PWM control function is implemented by the DC-DC converter PrimeCell (PL160). Refer to the ARM PrimeCell DC-DC Converter Interface (PL160) Technical Reference Manual for information about this device. The DC-DC PrimeCell uses the 4MHz IM_CLK signal to supply the DCDCCLK reference clock.

• Page 63: Stepper Motor Peripheral

  Stepper motor peripheral The example design instantiates two stepper controller blocks, each of which has two stepper motor controllers. Stepper A controls the Step 1 and 2 interfaces which are connected to the L298 stepper motor drivers. Stepper B controls the Step 3 and 4 interfaces which are connected at logic level to the connectors J21 and J22.
• Page 64 Reference Design Example 4.7.1 Stepper x control register The stepper controller control register defines the operating mode of the stepper. You must consider the maximum speed of the stepper motor when programming the step speed register or issuing consecutive single step commands in the stepper control register.
• Page 65 Bits ARM DUI 0163B Table 4-11 Stepper control register (continued) Name Access DOCOUNT Read/write SINGLESTEP Read/write Read/write Figure 4-3 Full-step two-phase output waveforms Figure 4-4 Full-step single-phase output waveforms Copyright © 2001-2003. All rights reserved. Reference Design Example Function Write a 1 to this bit to transfer the contents of the buffer register to the count and speed registers.
• Page 66 Reference Design Example 4.7.2 Stepx count register This is a 9-bit register that is used to specify the number of steps to advance. When the required number of steps are complete, the count stops and the register is loaded with the next value.

• Page 67: Gpio

  GPIO There are two 32-bit GPIO blocks instantiated in the example design. Each GPIO provides 32 general-purpose input and output signals that are connected to the connectors J16 and J17. GPIOB is also connected to the 38-way Mictor connector J7 for easy connection to a logic analyzer.
• Page 68 Reference Design Example 4.8.5 Data direction The GPIO_DIRN location is used to set the direction of each GPIO pin as follows: 1 = pin is an output 0 = pin is an input (default). Figure 4-6 shows the data direction control for one GPIO bit. 4-22 Data direction register Data register.

• Page 69: Ssram Interface

  SSRAM interface The SSRAM interface provides read and write access to the 1MB ZBT SSRAM on the logic module. Accesses take two system clock cycles for reads and writes. The interface supports word, halfword, and byte accesses to the SSRAM. ARM DUI 0163B Copyright ©.

• Page 70: Vectored Interrupt Controller

  Reference Design Example 4.10 Vectored interrupt controller The interrupt controller used in the example design is the Vectored Interrupt Controller (VIC) PrimeCell (PL190). Refer to the ARM PrimeCell Vectored Interrupt Controller (PL190) Technical Reference Manual for information about this device. The assignment of interrupt sources to the VIC are shown in Table 4-13.
• Page 71 Reference Design Example The SSP interrupt is the combined interrupt from the SSP PrimeCell. Refer to ARM PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual for details of the interrupt sources. The STEP1, STEP2, STEP3, and STEP4 interrupts are set active when the buffer registers of the corresponding stepper motor controller are empty.

• Page 72: Can Controller Interface

  Reference Design Example 4.11 CAN controller interface The CAN controller interface gives you access to the internal registers and reset signals of the Bosch CC770 CAN controllers. The offset addresses of CAN controller interfaces are shown in Table 4-14. Offset address 0x000000 0x100000.

• Page 73: Adc And Dac Interface

  4.12 ADC and DAC interface This interface gives you access to the ADCs and DAC. The interface also contains a status and control register. The offset addresses of the ADC and DAC interface are shown in Table 4-16. Offset address 0x000000 0x000004 0x100000.

• Page 74: Peripheral Information Block

  For example, revision v1.2 is represented by Note read_pib.axf Copyright © 2001-2003. All rights reserved. Table 4-18 PIB entry format is assigned, where 0xFFnn 0xFFFF is a special case 0x12 , supplied on the IM-AD1 CD, to display ARM DUI 0163B 0x00000000.
• Page 75 Appendix A Signal Descriptions This appendix describes the Integrator/IM-AD1 interface connectors and signal connections. It contains the following sections: • EXPA on page A-2 • EXPB on page A-4 • EXPIM on page A-6 • Logic analyzer connector on page A-8 •.

• Page 76: Appendix A Signal Descriptions

  Signal Descriptions EXPA Figure A-1 shows the pin numbers of the EXPA socket. The socket is viewed as if looking down through the stack. Copyright © 2001-2003. All rights reserved. Figure A-1 EXPA socket pin numbering ARM DUI 0163B.
• Page 77 The signals present on the EXPA connector are described in Table A-1. Pin label A[31:0] B[31:0] C[31:0] D[31:0] ARM DUI 0163B Signal Not used B[31:0] Not used Not used Copyright © 2001-2003. All rights reserved. Signal Descriptions Table A-1 AHB signal assignment Description These signals connect to the FPGA on the logic module.

• Page 78: Expb

  Signal Descriptions EXPB Figure A-2 shows the pin numbers of the socket EXPB on the underside of the interface module. Copyright © 2001-2003. All rights reserved. -12V -12V -12V Figure A-2 EXPB socket pin numbering ARM DUI 0163B.
• Page 79 Table A-2 describes the signals on the pins labeled F[31:0], H[31:0], and J[16:0]. Pin label F[31:24] F[23:0] H[31:29] H[27:0] J[15:14] J[3:0] ARM DUI 0163B Name Not used F[23:0] Not used SYSCLK Not used Not used nCFGEN nSRST Not used RTCK Not used nTRST Not used.

• Page 80: Expim

  Signal Descriptions EXPIM This connector is the same type of as that used for EXPA. Figure A-3 shows the pin numbers for EXPIM. Figure A-3 EXPIM connectors pin numbering Copyright © 2001-2003. All rights reserved. IM_A0 IM_B0 IM_A1 IM_B1 IM_A2 IM_B2 IM_B3 IM_A3.
• Page 81 LM-EP20K1000E Description IM_5BANK[59:0] FPGA input/output pins. IM_6BANK[53:0] FPGA input/output pins. Not used IM_CLK Clock signal from IM-AD1 to the logic module FPGA. Not used VCCO_5 Configurable voltage power supply rail. Not used (socket). VCCO_5 Configurable voltage power supply rail. Not used (socket).

• Page 82: Logic Analyzer Connector

  Signal Descriptions Logic analyzer connector A Mictor-type logic analyzer connector is provided. It connects to the B[31:0] signals used for GPIO B. If particular signals must be connected to a logic analyzer, the FPGA configuration can be changed to reassign the signal connections. If the FPGA configuration is changed to reassign signal connections, the GPIO B connections on connector J16 also change.
• Page 83 Table A-4 shows the pinout of the logic analyzer connector. ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Signal Descriptions Table A-4 J7 connector pinout Signal Signal No connect No connect No connect SYSCLK CLK_1.

• Page 84: Multi-ice (jtag

  Signal Descriptions Multi-ICE (JTAG) Figure A-5 shows the pinout of the Multi-ICE connector J21. For a description of the JTAG signals, see the user guide for your logic module. A-10 Copyright © 2001-2003. All rights reserved. nTRST RTCK nSRST Figure A-5 Multi-ICE connector pinout ARM DUI 0163B.

• Page 85: Appendix B Mechanical Specification

  Appendix B Mechanical Specification This appendix contains the mechanical specification for Integrator/IM-AD1. It contains the following section: • Mechanical information on page B-2 • Connector reference on page B-4. ARM DUI 0163B Copyright © 2001-2003. All rights reserved.

• Page 86: Mechanical Information

  Table B-1 on page B-4 for details on connector type, part numbers, and manufacturers. The Integrator/IM-AD1 is designed to be stackable (as the top card). Figure B-2 on page B-3 shows the dimensions for the connectors on the bottom side of the board as viewed from the top side of the board.
• Page 87 Mechanical Specification Figure B-2 Bottom board dimensions (viewed from top side) ARM DUI 0163B Copyright © 2001-2003. All rights reserved.

• Page 88: Connector Reference

  Mechanical Specification Connector reference Table B-1 lists the connectors on the IM-AD1. Two Weidmuller BL3.5/6 SN OR plugs and two BL3.5/4 SN OR plugs are supplied in a separate plastic bag. These mate with J10, J14, J19, and J23. Reference Type CON34_0.1'_34W_RA.
• Page 89 Glossary This glossary lists all the abbreviations used in the Integrator/IM-AD1 User Guide. Analog to Digital Converter. A device that converts an analog signal into digital data. Advanced High Performance Bus. The ARM open standard for high-performance on-chip buses. Advanced Peripheral Bus. The ARM open standard for lower-speed peripherals.
• Page 90 Glossary Synchronous Serial Port. Universal Asynchronous Receiver/Transmitter. UART Universal Serial Bus. Voltage Controlled Oscillator. Vectored Interrupt Controller. Zero Bus Turnaround Synchronous Static Random Access Memory. ZBT SSRAM Glossary-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
• Page 91 Index The items in this index are listed in alphabetical order, with symbols and numerics appearing at the end. The references given are to page numbers. ADC and DAC interface architecture 3-18 ADC and DAC interface registers 4-27 ADC connector 3-20 ADC, sampling rate 1-4 APB register peripheral 4-8 Architecture.
• Page 92 Index GPIO 4-21 GPIO connector 3-12 GPIO interface 3-12 GPIO registers GPIO_DATACLR 4-21 GPIO_DATAIN 4-21 GPIO_DATAOUT 4-21 GPIO_DATASET 4-21 GPIO_DIRN 4-22 Identifying the connectors 1-2 IMCLK signal 3-19, 4-16, 4-17 Integrator memory map 4-5 Interrupt assignment 4-24 Logic analyzer connector A-8 Logic module FPGA configuration 2-3 Logic module registers 4-8 Logic module, address assignment 4-5.